EPM240 Datasheet, PDF (25/86 Pages) Altera Corporation – JTAG & In-System Programmability

Chapter 2: MAX II Architecture
Global Signals
2–17
Figure 2–13. Global Clock Generation
GCLK0
GCLK1
GCLK2
GCLK3
Logic Array(1)
4
4
Global Clock
Network
Note to Figure 2–13:
(1) Any I/O pin can use a MultiTrack interconnect to route as a logic array-generated global clock signal.
The global clock network drives to individual LAB column signals, LAB column
clocks [3..0], that span an entire LAB column from the top to the bottom of the device.
Unused global clocks or control signals in a LAB column are turned off at the LAB
column clock buffers shown in Figure 2–14. The LAB column clocks [3..0] are
multiplexed down to two LAB clock signals and one LAB clear signal. Other control
signal types route from the global clock network into the LAB local interconnect. See
“LAB Control Signals” on page 2–5 for more information.
© October 2008 Altera Corporation
MAX II Device Handbook