EPM240 Datasheet, PDF (69/86 Pages) Altera Corporation – JTAG & In-System Programmability

Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
5–11
f For more explanations and descriptions about each internal timing microparameters
symbol, refer to the Understanding Timing in MAX II Devices chapter in the MAX II
Device Handbook.
Table 5–15. LE Internal Timing Microparameters
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
Symbol
Parameter
Min Max Min Max Min Max Min Max Min Max Unit
t_LUT
LE combinational LUT
delay
— 571 — 742 — 914 — 1,215 — 2,247 ps
t_COMB
Combinational path delay
— 147 — 192 — 236 — 243 — 305 ps
t_CLR
LE register clear delay
238 — 309 — 381 — 401 — 541 — ps
t_PRE
LE register preset delay
238 — 309 — 381 — 401 — 541 — ps
t_SU
LE register setup time
before clock
208 — 271 — 333 — 260 — 319 — ps
t_H
LE register hold time after 0 — 0 — 0 — 0 — 0 — ps
clock
t_CO
LE register clock-to-output — 235 — 305 — 376 — 380 — 489 ps
delay
t_CLKHL Minimum clock high or low 166 — 216 — 266 — 253 — 335 — ps
time
t_C
Register control delay
— 857 — 1,114 — 1,372 — 1,356 — 1,722 ps
Table 5–16. IOE Internal Timing Microparameters (Part 1 of 2)
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
Symbol
Parameter
Min Max Min Max Min Max Min Max Min Max Unit
t_FASTIO
Data output delay from
adjacent LE to I/O block
— 159 — 207 — 254 — 170 — 348 ps
t_IN
I/O input pad and buffer
— 708 — 920 — 1,132 — 907 — 970 ps
delay
t_GLOB (1)
I/O input pad and buffer
delay used as global signal
pin
— 1,519 — 1,974 — 2,430 — 2,261 — 2,670 ps
t_IOE
Internally generated output — 354 — 374 — 460 — 530 — 966 ps
enable delay
t_DL
t_OD (2)
Input routing delay
— 224 — 291 — 358 — 318 — 410 ps
Output delay buffer and pad — 1,064 — 1,383 — 1,702 — 1,319 — 1,526 ps
delay
© Novermber 2008 Altera Corporation
MAX II Device Handbook