EPM240 Datasheet, PDF (54/86 Pages) Altera Corporation – JTAG & In-System Programmability

4–4
Chapter 4: Hot Socketing and Power-On Reset in MAX II Devices
Hot Socketing Feature Implementation in MAX II Devices
Figure 4–2. Transistor-Level Diagram of MAX II Device I/O Buffers
IOE Signal
VPAD
IOE Signal or the
Larger of VCCIO or VPAD
The Larger of
VCCIO or VPAD
VCCIO
Ensures 3.3-V
Tolerance and
Hot-Socket
Protection
n+
n+
p - well
p+
p+
n+
n - well
p - substrate
The CMOS output drivers in the I/O pins intrinsically provide electrostatic discharge
(ESD) protection. There are two cases to consider for ESD voltage strikes: positive
voltage zap and negative voltage zap.
A positive ESD voltage zap occurs when a positive voltage is present on an I/O pin
due to an ESD charge event. This can cause the N+ (Drain)/ P-Substrate junction of
the N-channel drain to break down and the N+ (Drain)/P-Substrate/N+ (Source)
intrinsic bipolar transistor turn on to discharge ESD current from I/O pin to GND.
The dashed line (see Figure 4–3) shows the ESD current discharge path during a
positive ESD zap.
Figure 4–3. ESD Protection During Positive Voltage Zap
I/O
Source
PMOS
Gate
D
N+
Drain
I/O
Drain
P-Substrate
G
NMOS
Gate
S
N+
Source
GND
GND
MAX II Device Handbook
© October 2008 Altera Corporation