EPM240 Datasheet, PDF (73/86 Pages) Altera Corporation – JTAG & In-System Programmability

Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
5–15
Table 5–21. UFM Block Internal Timing Microparameters (Part 2 of 2)
–3 Speed –4 Speed –5 Speed –6 Speed –7 Speed
Grade
Grade
Grade
Grade
Grade
Symbol
Parameter
t_OE
Delay from data register clock to
data register output
t_RA
Maximum read access time
t_OSCS
Maximum delay between the
OSC_ENA rising edge to the
erase/program signal rising edge
t_OSCH
Minimum delay allowed from the
erase/program signal going low to
OSC_ENA signal going low
Min Max Min Max Min Max Min Max Min Max Unit
180 — 180 — 180 — 180 — 180 — ns
— 65 — 65 — 65 — 65 — 65 ns
250 — 250 — 250 — 250 — 250 — ns
250 — 250 — 250 — 250 — 250 — ns
© Novermber 2008 Altera Corporation
MAX II Device Handbook