AK4649 Datasheet, PDF (92/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK-AMP

[AK4649]
■ Stop of Clock
Master clock can be stopped when ADC, DAC, Digital MIC and Programmable Filter are not used.
1. PLL Master Mode
PMPLL bit
(Addr:01H, D0)
MCKO bit
(Addr:01H, D1)
External MCKI
"0" or "1"
Input
(1)
(2)
(3)
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
(1) (2) Addr:01H, Data:08H
(3) Stop an external MCKI
Figure 64. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop MCKO clock: MCKO bit = “1” → “0”
(3) Stop an external master clock.
2. PLL Slave Mode (LRCK or BICK pin)
PMPLL bit
(Addr:01H, D0)
External BICK
External LRCK
(1)
(2)
Input
(2)
Input
Example
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
(1) Addr:01H, Data:00H
(2) Stop the external clocks
Figure 65. Clock Stopping Sequence (2)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external BICK and LRCK clocks
MS1023-E-01
- 92 -
2010/08