AK4649 Datasheet, PDF (30/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK-AMP

[AK4649]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
The AK4649 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from the
MCKI pin, the internal PLL circuit is not operated. The clock required to operate the AK4649 is MCKI (256fs, 512fs or
1024fs). The input frequency of MCKI is selected by FS1-0 bits (Table 13).
Mode
FS3-2 bits
FS1 bit FS0 bit
MCKI Input
Frequency
Sampling Frequency
Range
0
x
0
0
256fs
7.35kHz ∼ 48kHz (default)
1
x
0
1
1024fs
7.35kHz ∼ 13kHz
2
x
1
0
512fs
7.35kHz ∼ 26kHz
3
x
1
1
256fs
7.35kHz ∼ 48kHz
Table 13. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) (x: Don’t care)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through LOUT/ROUT pins at fs=8kHz is shown in Table 14.
MCKI
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83dB
512fs
95dB
1024fs
96dB
Table 14. Relationship between MCKI and S/N of LOUT/ROUT pins
MCKI must always be present whenever the ADC, DAC or Programmable Filter is in operation (PMADL bit = “1”,
PMADR bit = “1”, PMDAC bit = “1” or PMPFIL bit = “1”). If MCKI is not provided, the AK4649 may draw excess
current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not
present, the ADC, DAC and Programmable Filter should be in the power-down mode (PMADL=PMADR=PMDAC=
PMPFIL bits = “0”).
AK4649
MCKO
MCKI
BICK
LRCK
SDTO
SDTI
256fs, 512fs or 1024fs
DSP or μP
MCLK
32fs or 64fs
BCLK
1fs
LRCK
SDTI
SDTO
Figure 19. EXT Master Mode
BCKO bit BICK Output Frequency
0
32fs
(default)
1
64fs
Table 15. BICK Output Frequency at Master Mode
MS1023-E-01
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2010/08