AK4649 Datasheet, PDF (25/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK-AMP

[AK4649]
■ PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, the LRCK and BICK pins go to “L” and irregular frequency clock is output from the MCKO pin at MCKO
bit is “1” before the PLL goes to lock state after PMPLL bit = “0” Æ “1”. If MCKO bit is “0”, the MCKO pin goes to “L”
(Table 7).
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
When sampling frequency is changed, the BICK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
PLL State
MCKO pin
BICK pin
MCKO bit = “0” MCKO bit = “1”
LRCK pin
After PMPLL bit “0” → “1”
“L” Output
Invalid
“L” Output
“L” Output
PLL Unlock (except the case above) “L” Output
Invalid
Invalid
Invalid
PLL Lock
“L” Output
Table 9
Table 10
1fs Output
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from the MCKO pin before the PLL goes to lock state after PMPLL bit = “0” →
“1”. Then, the clock selected by Table 9 is output from the MCKO pin when PLL is locked. ADC and DAC output invalid
data when the PLL is unlocked. For DAC, the output signal can be muted by writing “0” to DACL and DACS bits.
PLL State
MCKO pin
MCKO bit = “0” MCKO bit = “1”
After PMPLL bit “0” → “1”
“L” Output
Invalid
PLL Unlock (except the case above) “L” Output
Invalid
PLL Lock
“L” Output
Output
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
MS1023-E-01
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2010/08