AK4649 Datasheet, PDF (80/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK-AMP

[AK4649]
SYSTEM DESIGN
Figure 54 shows the system connection diagram. An evaluation board (AKD4649) is available for fast evaluation as well
as suggestions for peripheral circuitry.
DSP
Digital Ground Analog Ground
0.1µ
10
VSS2 LRCK
SDTI
MCKO
VSS3
DVDD
MCKI
BICK
SDTO
SVDD
μP
CDTIO CCLK
CSN
SPP
SPN
Top View
PDN
I2C
ROUT
LOUT
Rp
Cp
Analog Supply
2.4∼3.6V
+
10µ
VCOC
VSS1
MPWR
LIN2
MIN
VCOM
AVDD
RIN1
LIN1
RIN2
0.1µ
0.1µ
+
2.2µ
0.1µ
C
C
C
C
C
Speaker
1µ 220
1µ 220
20k ^Lineout
20k
Mono Input
Microphone
Notes:
- VSS1, VSS2 and VSS3 of the AK4649 must be distributed separately from the ground of external controllers.
- All digital input pins must not be left floating.
- When the AK4649 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed.
- When the AK4649 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 4.
- When the AK4649 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, around 100kΩ pull-up resistor must be connected to LRCK and BICK pins of the AK4649.
Figure 54. System Connection Diagram (3-wire Serial Mode, Internal Resistance Mode; BPM bit = “1”)
MS1023-E-01
- 80 -
2010/08