AK4649 Datasheet, PDF (91/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK-AMP

[AK4649]
■ Stereo Line Output
FS3-0 bits _0,000
(Addr:05H, D5&D2-0)
(1)
DACL bit
(2)
(Addr:02H, D4)
1,111
(10)
DVOL7-0 bits
(Addr:0FH)
Digital Filter Path
(Addr:26H)
LOPS bit
(Addr:03H, D6)
PMDAC bit
(Addr:00H, D2)
PMBP bit
(Addr:00H, D5)
PMLO bit
(Addr:00H, D3)
LOUT pin
ROUT pin
FFH
00H
(3)
(4)
(5)
FFH
00H
(7)
(8)
(11)
(6)
>300 ms
(9)
Normal Output
>300 ms
Figure 63. Stereo Lineout Sequence
Example:
PLL, Master Mode
Audio I/F Format :MSB justified (ADC & DAC)
Sampling Frequency:44.1KHz
Digital Volume 3: 0dB
MGAIN1=SPKG1=SPKG0=BEEPL bits = “0”
Programmable Filter OFF
(1) Addr:05H, Data:27H
(2) Addr:02H, Data:10H
(3) Addr:0FH, Data:FFH
(4) Addr:26H, Data:00H
(5) Addr:03H, Data:40H
(6) Addr:00H, Data:6CH
(7) Addr:03H, Data:00H
Playback
(8) Addr:03H, Data:40H
(9) Addr:00H, Data:40H
(10) Addr:02H, Data:00H
(11) Addr:03H, Data:00H
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up the sampling frequency (FS3-0 bits). When the AK4646 is PLL mode, DAC and Stereo Line-Amp must
be powered-up in consideration of PLL lock time after the sampling frequency is changed.
(2) Set up the path of “DAC Æ Stereo Line Amp”: DACL bit = “0” Æ “1”
(3) Set up the output digital volume3 (Addr = 0FH)
(4) Set up the path of Programmable Filter (PFDAC, ADCPF and PFSDO bits) (Addr = 26H)
(5) Enter power-save mode of Stereo Line Amp: LOPS bit = “0” Æ “1”
(6) Power-up DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMBP = PMLO bits = “0” → “1”
LOUT and ROUT pins rise up to VCOM voltage after PMLO bit is changed to “1”. Rise time to 99% VCOM
voltage is 300ms (max) at C=1μF and R_L=10kΩ.
(7) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1” Æ “0”
LOPS bit must be set to “0” after LOUT and ROUT pins rise up. Stereo Line-Amp goes to normal operation by
setting LOPS bit to “0”.
(8) Enter power-save mode of Stereo Line-Amp: LOPS bit: “0” Æ “1”
(9) Power-down DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMBP = PMLO bits = “1” → “0”
LOUT and ROUT pins fall down to 1% VCOM voltage. Fall time is 300ms (max) at C=1μF and R_L=10kΩ.
(10) Disable the path of “DAC Æ Stereo Line-Amp”: DACL bit = “1” Æ “0”
(11) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1” Æ “0”
LOPS bit must be set to “0” after LOUT and ROUT pins fall down.
MS1023-E-01
- 91 -
2010/08