AK4649 Datasheet, PDF (44/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK-AMP

[AK4649]
■ ALC Operation
The ALC (Automatic Level Control) is operated by ALC block when ALC bit is “1”. When ADCPF bit is “1”, ALC
circuit operates at recording path. When ADCPF bit is “0”, ALC circuit operates at playback path. ALC1 bit controls
ON/OFF of ALC operation at recording path, and ALC2 bit controls of ON/OFF of ALC operation at playback path.
Note 37. In this section, VOL means IVL and IVR for recording path, OVL and OVR for playback path.
Note 38. In this section, ALC bit means ALC1 bit for recording path, ALC2 bit for playback path.
Note 39. In this section, REF means IREF for recording path, OREF for playback path.
1. ALC Limiter Operation
During ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level (Table 25), the VOL value
(same value for both L and R) is attenuated automatically by the amount defined by the ALC limiter ATT step (Table 26).
The VOL is then set to the same value for both channels.
When ZELMN bit = “0” (zero cross detection is enabled), the VOL value is changed by ALC limiter operation at the
individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing timeout
period of both ALC limiter and recovery operation (Table 27). When ALC output level exceeds full-scale at LFST bit =
“1”, VOL values are immediately (Period: 1/fs) changed in 1step(L/R common). When ALC output level is less than
full-scale, VOL values are changed at the individual zero crossing point of each channels or at the zero crossing timeout.
When ZELMN bit = “1” (zero cross detection is disabled), VOL value is immediately (period: 1/fs) changed by ALC
limiter operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits.
The attenuate operation is executed continuously until the input signal level becomes ALC limiter detection level (Table
25) or less. After completing the attenuate operation, unless ALC bit is changed to “0”, the operation repeats when the
input signal level exceeds LMTH1-0 bits.
LMTH1 bit
0
0
1
1
LMTH0 bit ALC Limiter Detection Level ALC Recovery Waiting Counter Reset Level
0
ALC Output ≥ −2.5dBFS
−2.5dBFS > ALC Output ≥ −4.1dBFS
1
ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
0
ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
1
ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
Table 25. ALC Limiter Detection Level / Recovery Counter Reset Level
(default)
ALC1 Limiter ATT Step
LMAT1 bit LMAT0 bit _{ALC1 Output ALC1 Output ALC1 Output}
≥ LMTH
≥ FS
≥ FS + 6dB
0
0
1
1
1
0
1
2
2
2
1
0
2
4
4
1
1
1
2
4
Table 26. ALC Limiter ATT Step
ALC1 Output
≥ FS + 12dB
1
(default)
2
8
8
MS1023-E-01
- 44 -
2010/08