AK4649 Datasheet, PDF (62/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK-AMP

[AK4649]
(2) I2C-bus Control Mode (I2C pin = “H”)
The AK4649 supports the fast-mode I²C-bus (max: 400kHz). Pull-up resistors at the SDA and SCL pins must be
connected to (DVDD+0.3)V or less voltage.
(2)-1. WRITE Operations
Figure 45 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by START condition.
HIGH to LOW transition on the SDA line while SCL is HIGH indicates START condition (Figure 51). After the START
condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W).
The most significant six bits of the slave address are fixed as “001001”. The next bit is CAD0 (device address bit). This
bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets these device address bits (Figure
46). If the slave address matches that of the AK4649, the AK4649 generates an acknowledge and the operation is
executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the
acknowledge clock pulse (Figure 52). A R/W bit value of “1” indicates that the read operation is to be executed. “0”
indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4649. The format is MSB first, and those most
significant 2-bits are fixed to zeros (Figure 47). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 48). The AK4649 generates an acknowledge after each byte is received. Data transfer is always
terminated by STOP condition generated by the master. LOW to HIGH transition on the SDA line while SCL is HIGH
defines STOP condition (Figure 51).
The AK4649 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4649
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 4FH prior to
generating stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of the data line
can only be changed when the clock signal on the SCL line is LOW (Figure 53) except for the START and STOP
conditions.
S
T
S
A
R/W="0"
T
R
O
T
P
SDA
Slave
S _Address
Sub
Address(n)
Data(n)
Data(n+1)
Data(n+x)
P
A
A
A
A
A
A
C
C
C
C
C
C
K
K
K
K
K
K
Figure 45. Data Transfer Sequence at I²C Bus Mode
0
0
1
0
0
1 CAD0 R/W
Figure 46. The First Byte
0
A6
A5
A4
A3
A2
A1
A0
Figure 47. The Second Byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 48. The Third Byte
MS1023-E-01
- 62 -
2010/08