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AK4649 Datasheet, PDF (61/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK-AMP | |||
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[AK4649]
â Serial Control Interface
(1) 3-wire Serial Control Mode
Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTIO). The data on this
interface consists of Read/Write, Register address (MSB first, 7bits) and Control data (MSB first, 8bits). Each bit is
clocked in on the rising edge (âââ) of CCLK. Data writing become available on the rising edge of CSN. When reading,
the CDTIO pin will be output mode at the falling edge of 8th CCLIC and outputs D7-D0. The output finishes on the rising
edge of CSN. The CDTIO is placed in a Hi-Z state except outputting data at read operation mode. Clock speed of CCLK
is 5MHz (max). The value of internal registers are initialized by the PDN pin = âLâ.
Note 45. Data reading is only available on the following addresses; 00H~11H, 24H~2BH, 30~31H. When reading the
address 12H â¼ 23H, 2C~2FH, 32H~7FH, the register values are invalid.
CSN
CCLK âHâ or âLâ
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
âHâ or âLâ
CDTIO âHâ or âLâ
A6 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 âHâ or âLâ
R/W:
A6-A0:
D7-D0:
READ/WRITE (â1â: WRITE, â0â: READ)
Register Address
Control data (Input) at Write Command
Output data (Output) at Read Command
Figure 44. Serial Control I/F Timing
MS1023-E-01
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2010/08
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