AK4649 Datasheet, PDF (58/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK-AMP

[AK4649]
■ Stereo Line Output (LOUT/ROUT pins)
When DACL bit is “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins which is single-ended. When
DACL bit is “0”, output signal is muted and LOUT/ROUT pins output VCOM voltage. The load impedance is 10kΩ
(min.). When the PMLO bit = LOPS bit = “0”, the stereo line output enters power-down mode and the output is
pulled-down to VSS1 by 100kΩ(typ). When the LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at
power-up/down can be reduced by changing PMLO bit when LOPS bit = “1”. In this case, output signal line should be
pulled-down to VSS1 by 20kΩ after AC coupled as Figure 41. Rise/Fall time is 300ms (max) at C=1μF and R_L=10kΩ.
When PMLO bit = “1” and LOPS bit = “0”, stereo line output is in normal operation.
LOVL bit set the gain of stereo line output.
“DACL bit” “LOVL1- bits”
DAC
LOUT pin
ROUT pin
LOPS
0
1
Figure 40. Stereo Line Output
PMLO
Mode
LOUT/ROUT pin
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to VCOM
Table 52. Stereo Line Output Mode Select
LOVL1-0 bits
Gain
00
0dB (default)
01
+2dB
10
+4dB
11
+6dB
Table 53. Stereo Line Output Volume Setting
(default)
LOUT 1μF
ROUT
220Ω
20kΩ
Figure 41. External Circuit for Stereo Line Output (when using Pop Noise Reduction Circuit)
MS1023-E-01
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2010/08