AK4649 Datasheet, PDF (82/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK-AMP

[AK4649]
CONTROL SEQUENCE
■ Clock Set up
When ADC, DAC, Digital MIC or Programmable Filter is powered-up, the clocks must be supplied.
1. PLL Master Mode
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
MCKO bit
(Addr:01H, D1)
PMPLL bit
(Addr:01H, D0)
MCKI pin
M/S bit
(Addr:01H, D3)
BICK pin
LRCK pin
MCKO pin
(1)
(2) (3)
(4)
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
(1) Power Supply & PDN pin = “L” Æ “H”
(5)
Input
10msec(max)
10msec(max)
(7)
(6)
Output
(8)
Output
(2)Addr:01H, Data:08H
Addr:04H, Data:4AH
Addr:05H, Data:27H
(3)Addr:00H, Data:40H
(4)Addr:01H, Data:0BH
MCKO, BICK and LRCK output
Figure 55. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDN pin = “L” → “H”
“L” time of 150ns or more is needed to reset the AK4649.
(2) DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits must be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” → “1”
VCOM must first be powered-up before the other block operates.
(4) In case of using MCKO output: MCKO bit = “1”
In case of not using MCKO output: MCKO bit = “0”
(5) PLL starts after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source, and PLL
lock time is 10ms (max).
(6) The AK4649 starts to output the LRCK and BICK clocks after the PLL became stable. Then normal operation
starts.
(7) The invalid frequency is output from the MCKO pin during this period if MCKO bit = “1”.
(8) The normal clock is output from the MCKO pin after the PLL is locked if MCKO bit = “1”.
MS1023-E-01
- 82 -
2010/08