AK4633EN Datasheet, PDF (79/83 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

[AK4633]
3. PLL Slave Mode (MCKI pin)
PMPLL bit
(Addr:01H, D0)
MCKO bit
(Addr:01H, D1)
External MCKI
(1)
(1)
(2)
Input
Example
: ^{Audio I/F Format : DSP Mode, BCKP = MSBS = “0”}
PLL Reference clock: MCKI
BICK frequency: 64fs
Sampling Frequency: 8kHz
(1) Addr:01H, Data:00H
(2) Stop the external clocks
Figure 59. Clock Stopping Sequence (3)
<Example>
(1) Power down PLL: PMPLL bit = “1”  “0”
Stop MCKO output: MCKO bit = “1”  “0”
(2) Stop the external master clock.
4. EXT Slave Mode
External MCKI
External BICK
External FCK
(1)
Input
(1)
Input
(1)
Input
Figure 60. Clock Stopping Sequence (4)
Example
: ^{Audio I/F Format :MSB justified(ADC and DAC)}
Input MCKI frequency:1024fs
Sampling Frequency:8kHz
(1) Addr:01H, Data:00H
(2) Stop the external clocks
<Example>
(1) Stop the external MCKI, BICK and FCK clocks.
■ Power Down
VCOM should be powered-down after the master clock is stopped if clocks are supplied when all blocks except for VCOM
are powered-down. The AK4633 is also powered-down by the PDN pin = “L”. In this case, the registers are initialized.
MS0447-E-06
- 79 -
2015/10