AK4633EN Datasheet, PDF (77/83 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

■ Mono Lineout
[AK4633]
FS3-0 bits
(Addr:05H,
D5, D2-0)
XXXX
(1)
XXXX
(11)
DACA bit
(2)
(Addr:02H, D4)
(3)
ADCPF bit
0 or 1
0
(Addr:03H, D0)
PFDAC bit
(Addr:03H, D1)
ALC2 bit
(Addr:07H, D6)
OVOL7-0 bits
(Addr:0AH, D7-0)
0 or 1
0 or 1
XXH
(4)
(5)
1
0
XXH
AOPS bit
(Addr:03H, D6)
PMDAC bit
(Addr:00H, D2)
PMPFIL bit
(Addr:00H, D7)
PMAO bit
(Addr:00H, D3)
AOUT pin
(6)
(8)
(7)
(9)
(12)
(10)
>300 ms
Normal Output
>300 ms
Figure 56. Mono Lineout Sequence
Example:
PLL, Master Mode
Audio I/F Format :DSP Mode, BCKP=MSBS= “0”
Sampling Frequency: 16kHz
Digital Volume: 0dB
(1) Addr:05H, Data:02H
(2) Addr:02H, Data:10H
(3) Addr:03H, Data:02H
(4) Addr:07H, Data:00H
(5) Addr:0AH, Data:91H
(6) Addr:03H, Data:42H
(7) Addr:00H, Data:CCH
(8) Addr:03H, Data:02H
Playback
(9) Addr:03H, Data:42H
(10) Addr:00H, Data:40H
(11) Addr:02H, Data:00H
(12) Addr:03H, Data:02H
<Example>
This sequence is an example of Digital Output Volume at manual mode.
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits).
DAC should be powered-up in consideration of PLL lock time.
(2) Set up the path of “DAC  Mono Line Amp”: DACA bit: “0”  “1”
(3) Set up the path: ADCPF bit = “0”, PFDAC bit = “1”
(4) Disable ALC2: ALC2 bit = “0”
(5) Set up the digital volume (Addr: 0AH)
(6) Enter the power-save-mode of AOUT: AOPS bit: “0”  “1”
(7) Power Up DAC, programming filter and mono lineout.
PMDAC bit = PMPFIL bit = PMAO bit = “0”  “1”
The AOUT pin powers up at rising edge. The rise time is 300ms(max) when C = 1F.
(8) Exit the power-save-mode of AOUT: AOPS bit: “1”  “0”
The setting should be done after the AOUT pin rises up. After the setting, the signal is output from the AOUT
pin.
(9) Enter the power-save-mode of AOUT: AOPS bit: “0”  “1”
(10) Power Down DAC, programmable filter and mono lineout.
PMDAC bit = PMPFIL bit = PMAO bit = “1”  “0”
The AOUT pin powers up at falling edge. The fall time is 300ms(max) when C = 1F.
(11) Disable the path of “DAC  Mono Line Amp”: DACA bit: “1”  “0”
(12) Exit the power-save-mode of AOUT: AOPS bit: “1”  “0”
The setting should be down after the AOUT pin falls down.
MS0447-E-06
- 77 -
2015/10