AK4633EN Datasheet, PDF (68/83 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

[AK4633]
3. When the external clock (MCKI pin) is used in PLL Slave mode.
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
PMPLL bit
(Addr:01H, D0)
MCKI pin
MCKO pin
BICK pin
FCK pin
(1)
(2) (3)
(4)
(5)
Input
40msec(max)
(6)
(7)
(8)
Output
Input
Example:
Audio I/F Format: DSP Mode, BCKP = MSBS = “0”
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 13.5MHz
MCKO : Enable
Sampling Frequency:16kHz
(1) Power Supply & PDN pin = “L”  “H”
(2)Addr:04H, Data:C8H
Addr:05H, Data:02H
(3)Addr:00H, Data:40H
(4)Addr:01H, Data:03H
MCKO output start
BICK and FCK input start
Figure 49. Clock Set Up Sequence (3)
<Example>
(1) After Power Up: PDN pin “L”  “H”
“L” time (1) of 150ns or more is needed to reset the AK4633.
(2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, MSBS, BCKP and M/S bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0”  “1”
VCOM should first be powered up before the other block operates.
(4) PLL Power Up: PMPLL bit “0”  “1”
(5) PLL lock time is 40ms(max) after the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin)
is supplied.
(6) The normal clock is output from the MCKO pin after PLL is locked.
(7) The invalid frequency is output from the MCKO pin during this period.
(8) BICK and FCK clocks should be synchronized with MCKO clock.
MS0447-E-06
- 68 -
2015/10