AK4633EN Datasheet, PDF (28/83 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

[AK4633]
When PLL2 bit is “0”(PLL reference clock input is FCK or BICK pin), the sampling frequency is selected by FS3-2 bits
(Table 6).
Mode
0
1
2
Others
FS3 bit FS2 bit
FS1 bit
FS0 bit Sampling Frequency Range
0
0
Don’t care Don’t care
7.35kHz  fs  12kHz
0
1
Don’t care Don’t care
12kHz < fs  24kHz
1
0
Don’t care Don’t care
24kHz < fs  48kHz
Others
N/A
Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1”
(default)
■ PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, until PLL is locked after PMPLL bit = “0”  “1”, BICK and FCK pins output “L” and invalid frequency
clock is output from the MCKO pin when MCKO bit is “1”. If MCKO bit is “0”, “L” is output from the MCKO pin. (Table
7)
In case that sampling frequency is changed, setting PMPLL bit to “0” could prevent unstable clocks, and BICK and FCK
pins output “L”.
PLL State
MCKO pin
MCKO bit = “0” MCKO bit = “1”
BICK pin
FCK pin
After that PMPLL bit “0”  “1” “L” Output
Invalid
“L” Output
“L” Output
PLL Unlock
“L” Output
Invalid
Invalid
Invalid
PLL Lock
“L” Output
256fs Output
See Table 9
1fs Output
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from the MCKO pin after PMPLL bit = “0”  “1” or when sampling frequency is
changed. After that, 256fs clock is output from the MCKO pin while PLL is locked. ADC and DAC output invalid data
while the PLL is unlocked. For DAC, this output signal should be muted by writing “0” to DACA and DACM bits in Addr
= 02H.
PLL State
MCKO pin
MCKO bit = “0” MCKO bit = “1”
After that PMPLL bit “0”  “1”
“L” Output
Invalid
PLL Unlock
“L” Output
Invalid
PLL Lock
“L” Output
256fs Output
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
MS0447-E-06
- 28 -
2015/10