AK4633EN Datasheet, PDF (27/83 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

[AK4633]
■ Master Mode/Slave Mode
The M/S bit selects either master or slave modes. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4633 is power-down mode (PDN pin = “L”) and exits reset state, the AK4633 is in slave mode. After exiting reset state,
the AK4633 becames master mode by changing M/S bit to “1”.
When the AK4633 is used in master mode, FCK and BICK pins are a floating state until M/S bit becomes “1”. FCK and
BICK pins of the AK4633 should be pulled-down or pulled-up by a resistor about 100k externally to avoid the floating
state.
M/S bit
Mode
0
Slave Mode
(default)
1
Master Mode
Table 3. Select Master/Salve Mode
■ PLL Mode
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0
and FS3-0 bits. The PLL lock time is shown in Table 4, whenever the AK4633 is supplied to a stable clocks after PLL is
powered-up (PMPLL bit = “0”  “1”) or sampling frequency changes.
1) Setting of PLL Mode
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
PLL Reference
Clock Input
Pin
Input
Frequency
R and C of VCOC
pin(Note 28)
R[] C[F]
0
0
0
0
0
FCK pin
1fs
6.8k
1
0
0
0
1
BICK pin
16fs
10k
2
0
0
1
0
BICK pin
32fs
10k
3
0
0
1
1
BICK pin
64fs
10k
4
0
1
0
0
MCKI pin 11.2896MHz 10k
5
0
1
0
1
MCKI pin 12.288MHz 10k
6
0
1
1
0
MCKI pin
12MHz
10k
7
0
1
1
1
MCKI pin
24MHz
10k
12
1
1
0
0
MCKI pin
13.5MHz
10k
13
1
1
0
1
MCKI pin
27MHz
10k
Others
Others
N/A
Note 28. The tolerance of R is 5%, C is 30%.
Table 4. Setting of PLL Mode (*fs: Sampling Frequency)
220n
4.7n
4.7n
4.7n
4.7n
4.7n
4.7n
4.7n
10n
10n
PLL
Lock
Time
(max)
160ms
2ms
2ms
2ms
40ms
40ms
40ms
40ms
40ms
40ms
(default)
2) Setting of sampling frequency in PLL Mode.
When PLL2 bit is “1” (PLL reference clock input is the MCKI pin), the sampling frequency is selected by FS2-0 bits as
defined in Table 5.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit Sampling Frequency
0
0
0
0
0
8kHz
(default)
1
0
0
0
1
12kHz
2
0
0
1
0
16kHz
3
0
0
1
1
24kHz
4
0
1
0
0
7.35kHz
5
0
1
0
1
11.025kHz
6
0
1
1
0
14.7kHz
7
0
1
1
1
22.05kHz
10
1
0
1
0
32kHz
11
1
0
1
1
48kHz
14
1
1
1
0
29.4kHz
15
1
1
1
1
44.1kHz
Others
Others
N/A
Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1”
MS0447-E-06
- 27 -
2015/10