AK4633EN Datasheet, PDF (52/83 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

[AK4633]
■ Speaker Output
The power supply voltage for Speaker-Amp SVDD can be set in the range of 2.2V to 4.0V. However, SVDD should be set
in the range of 2.6V to 3.6V, when 8 dynamic speaker is connected. If SVDD is more than 3.6V when 8 dynamic
speaker is connected to the AK4633, the output of Speaker-Amp should be restricted in consideration of maximum power
dissipation.
The output signal from DAC is input to the Speaker-amp. This Speaker-amp is a mono output controlled by BTL and the
gain of Speaker-Amp is set by SPKG1-0 bits. The output voltage depends on AVDD and SPKG1-0 bits.
SPKG1-0 bits
SPK-AMP Output Level[Vpp]
DAC =-4.1dBFS (Note 30)
Gain
(Note 31)
00
3.17
0dB
01
4.00
+2dB
10
5.03
+4dB
11
6.33
+6dB
Note 30. AVDD=3.3V. The output level is proportional to AVDD.
Note 31. The Gain with a reference of SPKG1-0 bits = “00”.
Note 32. The setting of SPKG1-0 bits = “01” is recommend when 8 dynamic speaker is connected.
The SPK-Amp Power is 250mW at 8 Load Resistance and 4.0Vpp output level.
Table 35. SPK-Amp Output Voltage and Gain
<Caution for using Piezo Speaker>
When a piezo speaker is used, resistances more than 10 should be connected between SPP/SPN pins and speaker in series
respectively as shown in Figure 41. Zener diodes should be connected between speaker and GND as shown in Figure 41, in
order to protect SPK-Amp of the AK4633 from the power that the piezo speaker outputs when the speaker is pressured.
Zener diodes of the following Zener voltage should be used.
92% of SVDD ≤ Zener voltage of Zener diodo(ZD of Figure 41) ≤ SVDD+0.3V
Ex) In case of SVDD = 3.8V: 3.5V ≤ ZD ≤ 4.1V
For example, Zener diode which Zener voltage is 3.9V(Min 3.7V, Max 4.1V) can be used.
SPK-Amp
ZD
10
SPP
SPN
10
ZD
Figure 41. Circuit of Speaker Output (using a piezo speaker)
MS0447-E-06
- 52 -
2015/10