AK4633EN Datasheet, PDF (56/83 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

[AK4633]
■ Register Definitions
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H Power Management 1 PMPFIL PMVCM PMBP PMSPK PMAO PMDAC
0
PMADC
Default
0
0
0
0
0
0
0
0
PMADC: ADC Block Power Control
0: Power down (default)
1: Power up
When the PMADC bit changes from “0” to “1”, the initialization cycle (1059/fs=133ms@8kHz when ADRST
bit = “0”) starts. After initializing, digital data of the ADC is output.
PMDAC: DAC Block Power Control
0: Power down (default)
1: Power up
PMAO: Mono Line Out Power Control
0: Power down (default)
1: Power up
PMSPK: Speaker Block Power Control
0: Power down (default)
1: Power up
PMBP: BEEP In Power Control
0: Power down (default)
1: Power up
Even if PMBP bit is “0”, the path is still connected between BEEP and AOUT/SPK-Amp. BEEPS and BEEPA
bits should be set to “0” to disconnect these paths.
PMVCM: VCOM Block Power Control
0: Power down (default)
1: Power up
PMPFIL: Programmable Filter Block(HPF/2 Band EQ/ALC) Control
0: Power down (default)
1: Power up
Each block can be powered-down respectively by writing “0” to each bit. When the PDN pin is “L”, all blocks are
powered-down.
When PMPLL and MCKO bits and all bits in 00H address are “0”, all blocks are powered-down. The registers remain
unchanged.
When any of the blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be “0” when PMPLL and
MCKO bits and all bits in 00H address are “0”.
When BEEP signal is output from Speaker-Amp (Signal path: BEEP pin  SPP/SPN pins) or Mono Lineout-Amp
(Signal path: BEEP pin  AOUT pin) only, the clocks may not be present. When ADC, DAC, ALC1 or ALC2 is in
operation, the clocks must always be present.
MS0447-E-06
- 56 -
2015/10