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AK4633EN Datasheet, PDF (75/83 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP | |||
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[AK4633]
<Example>
This sequence is an example of ALC2 setting at fs=16kHz. If the parameter of the ALC2 is changed, please refer to
âTable 33. Example of the ALC Setting (Playback)â.
At first, clocks should be supplied according to âClock Set Upâ sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4633 is PLL mode, DAC and Speaker-Amp should be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of âDAC ï SPK-Ampâ: DACS bit: â0â ï® â1â
(3) Set up the ALC2 Timer (Addr: 06H)
(4) Set up the REF value of ALC2 (Addr: 08H)
(5) Set up OVOL value at start ALC2 (Addr: 10H), RGAIN1 and LMTH1
(6) Set up LMTH0, RGAIN0, LMAT1-0, ZELM and ALC2 bits (Addr: 07H)
(7) Set up path of programmable filter and SPK-Amp gain:
PFDAC bit = â1â, ADCPF bit = â0â, SPKG1-0 bits = âXXâ
(8) Set up coefficient of programmable filter (HPF/EQ): Addr: 10H ï¾ 1FH
(9) Set up ON/OFF of programmable filter (HPF/EQ)
HPF bit is recommended to â1â.
(10) Power Up DAC, SPK and programmable filter:
PMDAC bit = PMSPK bit = PMPFIL bit = â0â ï® â1â
(11) Exit Speaker power-save-mode: SPPSN bit = â0â ï® â1â
SPPSN bit should be set to â1â at more than 1ms after PMSPK bit is set to â1â.
(12) Enter Speaker power-save-mode: SPPSN bit = â1â ï® â0â
(13) Disable the path of âDAC ï SPK-Ampâ: DACS bit = â1â ï® â0â
(14) Power Down DAC, Speaker and programmable filter: PMDAC bit = PMSPK bit = PMPFIL bit = â1â ï® â0â
MS0447-E-06
- 75 -
2015/10
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