AK4633EN Datasheet, PDF (29/83 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

[AK4633]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz , 12.288MHz, 13.5MHz, 24MHz or 27MHz) is input to the MCKI pin, the
MCKO, BICK and FCK clocks are generated by an internal PLL circuit. The MCKO output frequency is fixed to 256fs,
the output is enabled by MCKO bit. The BICK is selected among 16fs, 32fs or 64fs, by BCKO1-0 bits (Table 9).
In DSP mode, FCK output can select Duty 50% or High-output only during 1 BICK cycle (Note 10). Except DSP mode,
FCKO bit should be set “0”.
When the BICK output frequency is 16fs, the audio interface format supports only Mode 0 (DSP Mode).
AK4633
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 27MHz
DSP or P
MCKI
MCKO
BICK
FCK
SDTO
SDTI
256fs
16fs, 32fs, 64fs
1fs
MCLK
BCLK
FCK
SDTI
SDTO
Figure 18. PLL Master Mode
Mode
0
1
2
3
BCKO1
BCKO0
BICK Output
Frequency
0
0
16fs
(default)
0
1
32fs
1
0
64fs
1
1
N/A
Table 9. BICK Output Frequency at PLL Master Mode
Mode
FCKO
FCK Output
0
0
Duty = 50%
(default)
1
1
High Width = 1/fBCK
fBCK is the output frequency of BICK
Table 10. FCK Output at PLL Master Mode and DSP Mode
MS0447-E-06
- 29 -
2015/10