AK4633EN Datasheet, PDF (32/83 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

[AK4633]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
When PMPLL bit is “0” and M/S bit is “1”, the AK4633 becomes clock master mode(EXT Master Mode). Master clock is
input from MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or
1024fs). The input frequency of MCKI is selected by FS3-0 bits (Table 11). The output frequency of BICK is selected to
32fs or 64fs by setting BCKO1-0 bit (Table 14). FCK bit should be set to “0”.
Mode
0
1
2
3
FS3-2 bits
FS1 bit FS0 bit MCKI Input Sampling Frequency
Frequency
Range
Don’t care
0
0
256fs
7.35kHz  fs  48kHz (default)
Don’t care
0
1
1024fs
7.35kHz < fs  13kHz
Don’t care
1
0
512s
7.35kHz < fs  26kHz
Don’t care
1
1
256fs
7.35kHz < fs  48kHz
Table 13. Setting MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “1”)
External Master Mode does not support Mode 0 (DSP Mode) of Audio Interface Format.
MCKI should always be present whenever the ADC or DAC or Programmable Filter is in operation (PMADC bit = “1” or
PMDAC bit = “1” or PMPFIL bit = “1”). If MCKI is not provided, the AK4633 may draw excess current and it is not
possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC, DAC
and Programmable Filter should be in the power-down mode (PMADC bit =PMDAC bit = PMPFIL bit = “0”).
AK4633
MCKO
MCKI
BICK
FCK
SDTO
SDTI
256fs, 512fs or 1024fs
DSP or P
MCLK
32fs, 64fs
BCLK
1fs
FCK
SDTI
SDTO
Figure 22. EXT Master Mode
Mode
0
1
2
3
BCKO1
BCKO0
BICK Output
Frequency
0
0
N/A
(default)
0
1
32fs
1
0
64fs
1
1
N/A
Table 14. BICK Output Frequency at EXT Master Mode
MS0447-E-06
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2015/10