AK4633EN Datasheet, PDF (11/83 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

[AK4633]
Parameter
Min.
Typ.
Max.
Unit
Speaker-Amp Characteristics: DAC  SPP/SPN pins, ALC2=OFF, C_L=3F, R_serial=10 x 2, BTL, SVDD=3.8V
Output Voltage
SPKG1-0 bits = “11”
(-4.1dBFS)
-
6.33
-
Vpp
S/(N+D) (Note 13)
SPKG1-0 bits = “11”
(-4.1dBFS)
-
60
-
dB
Output Noise Level (Note 13) SPKG1-0 bits = “11”
-
-81
-
dBV
Load Impedance (Note 14)
50
-
-

Load Capacitance
-
-
3
F
BEEP Input: BEEP pin, External Input Resistance= 20k
Maximum Input Voltage (Note 15)
-
1.98
-
Vpp
Output Voltage (Input Voltage=0.6Vpp)
BEEP  SPP/SPN (SPKG1-0 bits = “00”)
0.625
1.25
1.875
Vpp
BEEP  AOUT
0.25
0.50
0.75
Vpp
Power Supplies
Power Up (PDN = “H”)
All Circuit Power-up: (Note 17)
AVDD+DVDD
fs=8kHz
-
8
-
mA
fs=48kHz
-
11
17
mA
SVDD: Speaker-Amp Normal Operation (SPPSN bit = “1”, No Output)
SVDD=3.3V
-
4
12
mA
Power Down (PDN = “L”) (Note 18)
AVDD+DVDD+SVDD
-
1
100
A
Note 8. It is a differential value of plus and minus input pin. Each input pins should be connected to the AC coupling
capacitance serially. The differential input is not permission when MGAIN2-0 bits are “000”. The Maximum input
voltage of MICP and MICN pins are proportional to AVDD voltage. Vin= |(MICP)  (MICN)| = 0.069 x AVDD
(max)@MGAIN2-0 bits = “001”,
0.035 x AVDD (max)@MGAIN2-0 bits = “010”, 0.017 x AVDD (max)@MGAIN2-0 bits = “011”,
0.346 x AVDD (max)@MGAIN2-0 bits = “100”, 0.218 x AVDD (max)@MGAIN2-0 bits = “101”,
0.138 x AVDD (max)@MGAIN2-0 bits = “110”, 0.098 x AVDD (max)@MGAIN2-0 bits = “111”,
ADC function is not assumed for using the exceeded input voltage.
Note 9. Output Voltage is proportional to AVDD voltage. Vout = 0.8 x AVDD (typ).
Note 10. Input Voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ).
Note 11. When PLL reference clock is input to the FCK pin in PLL Slave Mode, S/(N+D):MICADC is 75dB (typ) and
S/(N+D):DACAOUT is 75dB(typ).
Note 12. Output Voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ).
Note 13. In case of measuring between SPP pin and SPN pin directly.
Note 14. Load impedance is total impedance of series resistance and piezo speaker impedance at 1kHz in Figure 41. Load
capacitance is capacitance of piezo speaker. When piezo speaker is used, 10 or more series resistors should be
connected at both SPP and SPN pins, respectively.
Note 15. The maximum input voltage of the BEEP is proportional to AVDD voltage and external input resistance (Rin).
Vout = 0.6 x AVDD x Rin/20k(max).
Note 16. Output Voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ).
Note 17. In case of PLL Master Mode (MCKI=12.288MHz) and PMMP = PMADC = PMDAC = PMPFIL = PMSPK =
PMVCM = PMPLL = MCKO = PMAO = PMBP = PMMP = M/S =“1”. In this case, the output current of MPI pin
is 0mA.
When the AK4633 is EXT mode (PMPLL = MCKO = M/S = “0”), “AVDD+DVDD” is typically 6mA@fs=8kHz,
9mA@fs=48kHz.
Note 18. All digital inputs pins are fixed to DVDD or DVSS.
MS0447-E-06
- 11 -
2015/10