AK4633EN Datasheet, PDF (66/83 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

[AK4633]
CONTROL SEQUENCE
■ Clock Set up
When ADC, DAC and Programmable Filter are used, the clocks must be supplied.
1. In case of PLL Master Mode
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
MCKO bit
(Addr:01H, D1)
PMPLL bit
(Addr:01H, D0)
MCKI pin
M/S bit
(Addr:01H, D3)
BICK pin
FCK pin
MCKO pin
(1)
(2) (3)
(4)
(5)
Input
40msec(max)
(6)
(7)
Output
1msec (max)
40msec(max)
(8)
(9)
Output
Example:
Audio I/F Format: DSP Mode, BCKP = MSBS = “0”
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 13.5MHz
MCKO : Enable
Sampling Frequency:16kHz
(1) Power Supply & PDN pin = “L”  “H”
(2)Addr:01H, Data:08H
Addr:04H, Data:C8H
Addr:05H, Data:02H
(3)Addr:00H, Data:40H
(4)Addr:01H, Data:0BH
MCKO, BICK and FCK output
Figure 47. Clock Set Up Sequence (1)
<Example>
(1) After Power Up: PDN pin = “L”  “H”
“L” time (1) of 150ns or more is needed to reset the AK4633.
(2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, MSBS, BCKP and M/S bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0”  “1”
VCOM should first be powered-up before the other block operates.
(4) In case of using MCKO output: MCKO bit = “1”
In case of not using MCKO output: MCKO bit = “0”
(5) PLL lock time is 40ms(max) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external
source.
(6) The AK4633 starts to output the FCK and BICK clocks after the PLL becomes stable. The normal operation of
the block which a clock is necessary for becomes possible.
(7) The invalid frequencies are output from FCK and BICK pins during this period.
(8) The invalid frequency is output from the MCKO pin during this period.
(9) The normal clock is output from the MCKO pin after the PLL is locked.
MS0447-E-06
- 66 -
2015/10