AK4633EN Datasheet, PDF (64/83 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

Differential Input
1k
1k
1µ
1µ
20k
10µ
220
+
1µ ^0.1µ
Analog Supply
2.24.0V
[AK4633]
2.2µ+
Analog Supply
2.23.6V _10µ +
0.1µ
0.1µ
Cp Rp
1 VCOM
2 AVSS
3 _AVDD
4 VCOC
5 PDN
6 CSN
Top View
R2
SPN 18
SPP 17 ^R1
ZD2
MCKO 16
MCKI 15
DVSS 14
DVDD 13 _0.1µ
Speaker
ZD1
Dynamic SPK :
R1,R2 : Short
ZD1,ZD2 : Open
Peizo SPK :
R1,R2 : 10
ZD1,ZD2 : Required
10
DSP or P
Figure 46. Typical Connection Diagram
Note:
- AVSS, DVSS and SVSS of the AK4633 should be distributed separately from the ground of external controllers.
- If AVDD and DVDD are separated, DVDD should be set from 1.6V to 3.6V.
- All digital input pins should not be left floating.
- When the AK4633 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of the VCOC pin are not needed.
- When the AK4633 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of the VCOC pin are shown in Table
36.
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
PLL Reference
Clock Input
Pin
Input
Frequency
Rp and Cp of
VCOC pin
PLL Lock
Rp[] Cp[F] ^{Time (max)}
0
0
0
0
0
FCK pin
1fs
6.8k 220n 160ms (default)
1
0
0
0
1
BICK pin
16fs
10k 4.7n
2ms
2
0
0
1
0
BICK pin
32fs
10k 4.7n
2ms
3
0
0
1
1
BICK pin
64fs
10k 4.7n
2ms
4
0
1
0
0
MCKI pin 11.2896MHz 10k 4.7n
40ms
5
0
1
0
1
MCKI pin 12.288MHz 10k 4.7n
40ms
6
0
1
1
0
MCKI pin
12MHz
10k 4.7n
40ms
7
0
1
1
1
MCKI pin
24MHz
10k 4.7n
40ms
12
1
1
0
0
MCKI pin
13.5MHz
10k 10n
40ms
13
1
1
0
1
MCKI pin
27MHz
10k 10n
40ms
Others
Others
N/A
Table 36. Setting of PLL Mode (*fs: Sampling Frequency)
MS0447-E-06
- 64 -
2015/10