AK4372 Datasheet, PDF (59/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4372]
SYSTEM DESIGN
Figure 50 shows the system connection diagram. The evaluation board [AKD4372] demonstrates the optimum layout,
power supply arrangements and measurement results.
Digital Ground
Analog Ground
µP
Audio
Controller
Cp Rp
1000p
VSS2 CCLK CSN PDN MUTET
1µ
VCOC MCKO CDTI LOUT ROUT
AK4372ECB
MCKI LRCK DVDD I2C VCOM
Top View
BICK LIN HPR AVDD
SDATA RIN MIN HPL VSS1
+
2.2µ
10
0.1µ
0.1µ
++
220µ
220µ
SPK-Amp
Analog Supply
+ _10µ
1.6∼3.6V
16Ω 16Ω
Headphone
Notes:
- VSS1 and VSS2 of the AK4372 should be distributed separately from the ground of external controllers.
- All digital input pins (I2C, SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN) must
not be left floating.
- When the AK4372 is in EXT mode (PMPLL bit = “0”), a resistor and capacitor for the VCOC pin are not
needed.
- When the AK4372 is in PLL mode (PMPLL bit = “1”), a resistor and capacitor for the VCOC pin are shown in
Table 4
- When the AK4372 is used in master mode, LRCK and BICK pins are floating before the M/S bit is changed to
“1”. Therefore, a 100kΩ pull-up resistor should be connected to the LRCK and BICK pins of the AK4372.
- When DVDD is supplied from AVDD via 10Ω series resistor, the capacitor larger than 0.1μF should not be
connected between DVDD and the ground.
Figure 50. Typical Connection Diagram (In case of AC coupling to MCKI)
MS0684-E-02
- 59 -
2008/12