AK4372 Datasheet, PDF (39/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4372]
„ Power-Up/Down Sequence (PLL Slave mode)
1) DAC → HP-Amp
Power Supply
PDN pin
(1)
>150ns
PMVCM, PMPLL,
PMDAC, MCKO bits
(2) >0s
Don’t care (3)
MCKI pin
MCKO pin
Unstable
(4) ~20ms
BICK,
LRCK pins
DAC Internal
State
SDTI pin
DALHL,
DARHR bits
Don’t care (5)
Unstable
PD
Don’t care
Normal Operation
Unstable
(6) >0s
PMHPL,
PMHPR bits
MUTEN bit
(7) >2ms
(12)
Don’t care
Don’t care
Don’t care
Unstable
(4) ~20ms
Unstable (5)
Don’t care
Unstable
PD
Unstable
Normal Operation
PD
Don’t care
(6) >0s
(7) >2ms
ATTL7-0
ATTR7-0 bits
HPL/R pin
00H(MUTE)
FFH(0dB)
(10) GD (11) 1061/fs (10) (11)
(8)
00H(MUTE)
(9)
(8)
FFH(0dB) _00H(MUTE)
(10)(11) (10) (11)
(9)
Figure 32. Power-up/down sequence of DAC and HP-amp (Don’t care: except Hi-Z)
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. The PDN pin should be set to “H” at least 150ns after power is supplied.
(2) PMVCM, PMPLL, PMDAC and MCKO bits should be changed to “1” after the PDN pin goes “H”.
(3) The PLL operation is executed when the system clock is input to the MCKI pin.
(4) The PLL lock time is referred to Table 4. After the PLL is locked, the MCKO pin outputs the master clock.
(5) The clocks (BICK, LRCK) generated by MCKO are needed to operate the DAC. When the PMDAC bit = “0”, these
clocks can be stopped. The headphone-amp can operate without these clocks.
(6) DALHL and DARHR bits should be changed to “1” after the PLL is locked.
(7) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin
is 2.2μF) after the DALHL and DARHR bits are changed to “1”.
(8) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to
VCOM/2 is t_r = 70k x C(typ). When C=1μF, t_r = 70ms(typ).
(9) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to
VCOM/2 is t_f = 60k x C(typ). When C=1μF, t_f = 60ms(typ).
PMHPL and PMHPR bits should be changed to “0” after HPL and HPR pins go to HVSS. After that, the
DALHL/DARHR bits should be changed to “0”.
(10) Analog output corresponding to the digital input has a group delay (GD) of 22/fs(=499μs@fs=44.1kHz).
(11) The ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
(12) The power supply should be switched off after the headphone-amp is powered down (HPL/R pins become “L”).
When AVDD and DVDD are supplied separately, DVDD should be powered-down at the same time or after AVDD.
MS0684-E-02
- 39 -
2008/12