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AK4372 Datasheet, PDF (47/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP | |||
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[AK4372]
â Serial Control Interface
(1) 3-wire Serial Control Mode (I2C pin = âLâ)
Internal registers may be written to via the 3-wire μP interface pins (CSN, CCLK and CDTI). The data on this interface
consists of the Chip address (2-bits, Fixed to â01â), Read/Write (1-bit, Fixed to â1â, Write only), Register address (MSB
first, 5-bits) and Control data (MSB first, 8-bits). Address and data are clocked in on the rising edge of CCLK. For write
operations, the data is latched after a low-to-high transition of the 16th CCLK. CSN should be set to âHâ once after 16
CCLKs for each address. The clock speed of CCLK is 5MHz(max). The value of the internal registers is initialized at the
PDN pin = âLâ.
CSN
CCLK
Clock, âHâ or âLâ
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Clock, âHâ or âLâ
CDTI âHâ or âLâ
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 âHâ or âLâ
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to â01â)
READ/WRITE (Fixed to â1â, Write only)
Register Address
Control Data
Figure 40. 3-wire Serial Control I/F Timing
MS0684-E-02
- 47 -
2008/12
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