AK4372 Datasheet, PDF (43/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4372]
„ Power-Up/Down Sequence (PLL Master mode)
1) DAC → HP-Amp
Power Supply
PDN pin
(1)
>150ns
M/S, PMVCM, PMPLL,
PMDAC, MCKO bits
(2) >0
Don’t care (3)
MCKI pin
MCKO pin
Unstable
(4) ~20ms
Don’t care “L”
BICK, LRCK pins
DAC Internal
State
SDTI pin
Unstable
PD
Don’t care
Normal Operation
DALHL,
DARHR bits
PMHPL,
PMHPR bits
Unstable
(5) >0
(6) >2ms
MUTEN bit
Don’t care
Don’t care
Unstable
(4) ~20ms
Unstable
Unstable
PD
Unstable
Normal Operation
(5) >0
(6) >2ms
(11)
Don’t care
Don’t care
PD
Don’t care
ATTL7-0
ATTR7-0 bits
HPL/R pin
00H(MUTE)
FFH(0dB)
(9) GD (10) 1061/fs (9) (10)
(7)
00H(MUTE)
(8)
(7)
FFH(0dB) 00H(MUTE)
(9) (10) (9) (10)
(8)
Figure 36 Power-up/down sequence of DAC and HP-amp (Don’t care: except Hi-Z)
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. The PDN pin should be set to “H” at least 150ns after power is supplied.
(2) PMVCM, PMPLL, PMDAC, MCKO and M/S bits should be changed to “1” after the PDN pin goes “H”.
(3) The PLL operation is executed when the system clock is input to the MCKI pin.
(4) The PLL lock time is referred to Table 4. After the PLL is locked, each clock is output from BICK, LRCK and
MCKO pins.
(5) DALHL and DARHR bits should be changed to “1” after the PLL is locked.
(6) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin
is 2.2μF) after the DALHL and DARHR bits are changed to “1”.
(7) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to
VCOM/2 is t_r = 70k x C(typ). When C=1μF, t_r = 70ms(typ).
(8) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to
VCOM/2 is t_f = 60k x C(typ). When C=1μF, t_f = 60ms(typ).
PMHPL and PMHPR bits should be changed to “0” after HPL and HPR pins go to HVSS. After that, the
DALHL/DARHR bits should be changed to “0”.
(9) Analog output corresponding to the digital input has group delay (GD) of 22/fs(=499μs@fs=44.1kHz).
(10) The ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
(11) The power supply should be switched off after the headphone-amp is powered down (HPL/R pins become “L”).
When AVDD and DVDD are supplied separately, DVDD should be powered-down at the same time or after AVDD.
MS0684-E-02
- 43 -
2008/12