AK4372 Datasheet, PDF (25/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4372]
LRCK
Lch
Rch
BICK
SDATA
16bit
SDATA
20bit
SDATA
24bit
15 14
19 18
23 22
0
410
Don’t
care
15 14
Dcaorne’t _{19 18}
0
410
Don’t
care
15 14
Don’t
care
19 18
8
3
4
1
0
Don’t
care
23 22
8
3
4
1
0
Don’t
care
23 22
Figure 19. Mode 2 Timing (LRP = BCKP bits = “0”)
LRCK
BICK
SDATA
16bit
SDATA
20bit
SDATA
24bit
Lch
Rch
15 14
0
19 18
410
Don’t
care
15 14
Don’t
care
19 18
0
410
Dcaorne’t
15
Don’t
care
19
23 22
8 3 4 1 0 ^{Dcaorne’t} 23 22
8 3 4 1 0 ^{Dcaorne’t}
23
BICK
(32fs)
SDATA
16bit
0 15 14
6 5 4 3 2 1 0 15 14
6 5 4 3 2 1 0 15
Figure 20. Mode 3 Timing (LRP = BCKP bits = “0”)
MS0684-E-02
- 25 -
2008/12