AK4372 Datasheet, PDF (42/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4372]
4) LIN/RIN/MIN → Lineout
Power Supply
PDN pin
PMVCM bit
(1) >150ns
(2) >0s
Don’t care
LINL, MINL,
RINR, MINR bits
PMLO bit
(3) >0s
(5) >2ms
(5) >2ms
LIN/RIN/MIN pins
(4)
(Hi-Z)
(Hi-Z)
LMUTE,
ATTS3-0 bits
10H(MUTE)
0FH(0dB)
(6)
LOUT/ROUT pins
(Hi-Z)
(6)
(6)
(Hi-Z)
Figure 35. Power-up/down sequence of LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 and Lineout
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. The PDN pin should be set to “H” at least 150ns after power is supplied. MCKI, BICK and LRCK can be
stopped when DAC is not used.
(2) PMVCM bit should be changed to “1” after the PDN pin is set to “H”.
(3) LINL, MINL, RINR and MINR bits should be changed to “1” after PMVCM bit is changed to “1”.
(4) When LINL, MINL, RINR or MINR bit is changed to “1”, the LIN, RIN or MIN pin is biased to 0.475 x AVDD.
(5) PMLO bit should be changed to “1” at least 2ms (in case external capacitance at the VCOM pin is 2.2μF) after LINL,
MINL, RINR and MINR bits are changed to “1”.
(6) When the PMLO bit is changed, pop noise is output from the LOUT/ROUT pins.
MS0684-E-02
- 42 -
2008/12