AK4372 Datasheet, PDF (16/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4372]
OPERATION OVERVIEW
■ System Clock
There are the following six clock modes to interface with external devices (Table 1 and Table 2).
Mode
PLL Master Mode
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: BICK pin)
PLL Slave Mode 3
(PLL Reference Clock: LRCK pin)
EXT Master Mode
EXT Slave Mode
PMPLL bit
1
1
M/S bit
1
0
1
0
1
0
0
1
0
0
Table 1. Clock Mode Setting (x: Don’t care)
PLL3-0 bits
See Table 4
See Table 4
See Table 4
See Table 4
x
x
Figure
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Mode
PLL Master Mode
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: BICK pin)
PLL Slave Mode 3
(PLL Reference Clock: LRCK pin)
EXT Master Mode
EXT Slave Mode
MCKO bit
0
1
0
1
0
MCKO pin
L
Selected by
PS1-0 bits
L
Selected by
PS1-0 bits
MCKI pin
Selected by
PLL4-0 bits
Selected by
PLL4-0 bits
L
GND
0
L
GND
0
L
Selected by
FS3-0 bits
0
L
Selected by
FS3-0 bits
Table 2. Clock pins state in Clock Mode
BICK pin
Output
(Selected by
BF bit)
Input
(32fs ∼ 64fs)
Input
(Selected by
PLL4-0 bits)
Input
(32fs ∼ 64fs)
Output
(Selected by
BF bit)
Input
(32fs ∼ 64fs)
LRCK pin
Output
(1fs)
Input
(1fs)
Input
(1fs)
Input
(1fs)
Output
(1fs)
Input
(1fs)
■ Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4372 is power-down mode (PDN pin = “L”) and exits reset state, the AK4372 is slave mode. After exiting reset state,
the AK4372 changes to master mode by setting M/S bit = “1”.
When the AK4372 is in master mode, the LRCK and BICK pins are a floating state until M/S bit becomes “1”. The LRCK
and BICK pins of the AK4372 should be pulled-down or pulled-up by a resistor (about 100kΩ) externally to avoid the
floating state.
M/S bit
Mode
0
Slave Mode
(default)
1
Master Mode
Table 3. Select Master/Slave Mode
MS0684-E-02
- 16 -
2008/12