AK4372 Datasheet, PDF (12/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4372]
Parameter
Symbol
min
typ
max
Units
Control Interface Timing (I²C Bus mode): (Note 28)
SCL Clock Frequency
fSCL
-
-
400
kHz
Bus Free Time Between Transmissions
tBUF
1.3
-
-
μs
Start Condition Hold Time (prior to first clock pulse) tHD:STA
0.6
-
-
μs
Clock Low Time
tLOW
1.3
-
-
μs
Clock High Time
tHIGH
0.6
-
-
μs
Setup Time for Repeated Start Condition
tSU:STA
0.6
-
-
μs
SDA Hold Time from SCL Falling (Note 29)
tHD:DAT
0
-
-
μs
SDA Setup Time from SCL Rising
tSU:DAT
0.1
-
-
μs
Rise Time of Both SDA and SCL Lines
tR
-
-
0.3
μs
Fall Time of Both SDA and SCL Lines
tF
-
-
0.3
μs
Setup Time for Stop Condition
tSU:STO
0.6
-
-
μs
Capacitive Load on Bus
Cb
-
-
400
pF
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
-
50
ns
Power-down & Reset Timing
PDN Pulse Width (Note 30)
tPD
150
-
-
ns
Note 22. Except AC coupling.
Note 23. Pulse width to ground level when the MCKI pin is connected to a capacitor in series and a resistor is connected
to ground. (Refer to Figure 3.)
Note 24. Refer to “Serial Data Interface”.
Note 25. Min is longer value between 312.5ns or 1/(64fs) except for PLL Mode, PLL4-0 bits = “01110”, “01111”.
Note 26. BICK rising edge must not occur at the same time as LRCK edge.
Note 27. CCLK rising edge must not occur at the same time as CSN edge.
Note 28. I²C is a registered trademark of Philips Semiconductors.
Note 29. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 30. When power-up, the AK4372 can be reset by bringing PDN pin = “H” from “L”.
MS0684-E-02
- 12 -
2008/12