AK4372 Datasheet, PDF (41/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4372]
3) LIN/RIN/MIN → HP-Amp
Power Supply
PDN pin
PMVCM bit
(1) >150ns
(2) >0s
LINHL, MINHL,
RINHR, MINHR bits
PMHPL/R bits
(3) >0s
(5) >2ms
Don’t care
(5) >2ms
MUTEN bit
LIN/RIN/MIN pins
HPL/R pins
(4)
(Hi-Z)
(6)
(Hi-Z)
(7)
(6)
Figure 34. Power-up/down sequence of LIN/RIN/MIN and HP-Amp
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. The PDN pin should be set to “H” at least 150ns after power is supplied. MCKI, BICK and LRCK can be
stopped when DAC is not used.
(2) PMVCM bit should be changed to “1” after the PDN pin is set to “H”.
(3) LINHL, MINHL, RINHR and MINHR bits should be changed to “1” after PMVCM bit is changed to “1”.
(4) When LINHL, MINHL, RINHR or MINHR bit is changed to “1”, the LIN, RIN or MIN pin is biased to 0.475 x
AVDD.
(5) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at the
VCOM pin is 2.2μF) after LINHL, MINHL, RINHR and MINHR bits are changed to “1”.
(6) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to
VCOM/2 is t_r = 70k x C(typ). When C=1μF, t_r = 70ms(typ).
(7) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to
VCOM/2 is t_f = 60k x C(typ). When C=1μF, t_f = 60ms(typ).
PMHPL and PMHPR bits should be changed to “0” after the HPL and HPR pins settle to VSS1. After that, the
LINHL, MINHL, RINHR and MINHR bits should be changed to “0”.
MS0684-E-02
- 41 -
2008/12