AK4372 Datasheet, PDF (33/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4372]
■ Stereo Line Output (LOUT, ROUT pins)
The common voltage is 0.475 x AVDD. The load resistance is 10kΩ(min). When the PMLO bit is “1”, the stereo line
output is powered-up. DALL, LINL, RINL and MINL bits control each path switch of LOUT. DARR, LINR, RINR and
MINR bits control each path switch of ROUT. When LM bit = “0”, LOG bit = “0” (R_1L = R_2L = R_DL = 100k) and ATTS3-0
bits is “0FH”(0dB), the mixing gain is 0dB(typ) for all paths. When the LOG bit = “1”(R_DL= 50k), the DAC path gain is
+6dB. When LM bit = “1”, LIN and RIN signals are output from LOUT/ROUT pins as (L+R)/2 respectively.
If the path is OFF and the signal is input to the input pin, the input pin should be biased to a voltage equivalent to VCOM
voltage (= 0.475 x AVDD) externally. Figure 51 shows the external bias circuit example.
LIN pin
RIN pin
MIN pin
DAC Lch
R1L
LINL bit
R1L
RINL bit
R2L
MINL bit
RDL
DALL bit
100k(typ)
−
RL
+
RL
−
+
LOUT pin
LIN pin
RIN pin
MIN pin
DAC Rch
R1L
LINR bit
R1L
RINR bit
R2L
MINR bit
RDL
DARR bit
100k(typ)
−
RL
+
RL
−
+
ROUT pin
Figure 26. Summation circuit for stereo line output
MS0684-E-02
- 33 -
2008/12