AK4372 Datasheet, PDF (23/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4372]
Mode FS3
FS2
FS1
FS0
fs
MCKI
0
0
0
0
0
8kHz ∼ 48kHz
256fs
1
0
0
0
1
8kHz ∼ 48kHz
512fs
2
0
0
1
0
8kHz ∼ 24kHz
1024fs
4
0
1
0
0
8kHz ∼ 48kHz
256fs
5
0
1
0
1
8kHz ∼ 48kHz
512fs
6
0
1
1
0
8kHz ∼ 24kHz
1024fs
8
1
0
0
0
8kHz ∼ 48kHz
256fs
(default)
9
1
0
0
1
8kHz ∼ 48kHz
512fs
10
1
0
1
0
8kHz ∼ 24kHz
1024fs
12
1
1
0
0
8kHz ∼ 48kHz
384fs
13
1
1
0
1
8kHz ∼ 24kHz
768fs
Others
Others
N/A
N/A
Table 11. Relationship between Sampling Frequency and MCKI Frequency (EXT mode) (N/A: Not available)
PS1
PS0
MCKO
0
0
256fs (default)
0
1
128fs
1
0
64fs
1
1
32fs
Table 12. MCKO frequency (EXT mode, MCKO bit = “1”)
MCKI
pin
MCKO
pin
BICK
pin
LRCK
pin
Master Mode (M/S bit = “1”)
Power Up (PMDAC bit = “1”)
Power Down (PMDAC bit = “0”)
Refer to Table 11
Input or
fixed to “L” or “H” externally
MCKO bit = “0”: L
MCKO bit = “1”: Output
L
BF bit = “1”: 64fs output
BF bit = “0”: 32fs output
L
Output
L
Table 13. Clock Operation in Master mode (EXT mode)
MCKI pin
MCKO pin
BICK pin
LRCK pin
Slave Mode (M/S bit = “0”)
Power Up (PMDAC bit = “1”)
Power Down (PMDAC bit = “0”)
Refer to Table 11
Input or
fixed to “L” or “H” externally
MCKO bit = “0”: L
MCKO bit = “1”: Output
L
Input
Fixed to “L” or “H” externally
Input
Fixed to “L” or “H” externally
Table 14. Clock Operation in Slave mode (EXT mode)
For low sampling rates, DR and S/N degrade because of the out-of-band noise. DR and S/N are improved by using higher
frequency for MCKI. Table 15 shows DR and S/N when the DAC output is to the HP-amp.
MCKI
DR, S/N (BW=20kHz, A-weight)
fs=8kHz
fs=16kHz
256fs/384fs/512fs
56dB
75dB
768fs/1024fs
75dB
90dB
Table 15. Relationship between MCKI frequency and DR (and S/N) of HP-amp (2.4V)
MS0684-E-02
- 23 -
2008/12