AK4372 Datasheet, PDF (44/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4372]
2) DAC → Lineout
Power Supply
PDN pin
(1) >150ns
M/S, PMVCM, PMPLL, ⁽²⁾
PMDAC, MCKO bits
>0
MCKI pin
Don’t care (3)
MCKO pin
Unstable
(4) ~20ms
Don’t care “L”
BICK, LRCK pins
DAC Internal
State
SDTI pin
PD
Don’t care
Unstable
Unstable
DALL,
DARR bits
PMLO bit
(5) >0
(6) >0
ATTL/R7-0 bits
00H(MUTE)
Don’t care
Don’t care
Unstable
(4) ~20ms
Unstable
Normal Operation
Unstable
PD
Unstable
Normal Operation
FFH(0dB)
(5) >0
(6) >0
00H(MUTE)
FFH(0dB)
LMUTE,
ATTS3-0 bits
10H(MUTE)
(8) GD (9) 1061/fs
0FH(0dB)
(8) (9)
(8) (9)
(7)
LOUT/ROUT pins
(Hi-Z)
(8)
(7)
(Hi-Z)
Figure 37. Power-up/down sequence of DAC and LOUT/ROUT(Don’t care: except Hi-Z)
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. The PDN pin should be set to “H” at least 150ns after power is supplied.
(2) PMVCM, PMPLL, PMDAC, MCKO and M/S bits should be changed to “1” after the PDN pin goes “H”.
(3) The PLL operation is executed when the system clock is input to the MCKI pin.
(4) The PLL lock time is referred to Table 4. After the PLL is locked, each clock is output from BICK, LRCK and
MCKO pins.
(5) DALL and DARR bits should be changed to “1” after the PLL is locked.
(6) PMLO bit is changed to “1”.
(7) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins.
(8) Analog output corresponding to the digital input has group delay (GD) of 22fs(=499μs@fs=44.1kHz).
(9) The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
MS0684-E-02
- 44 -
2008/12