AK4372 Datasheet, PDF (48/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4372]
(2) I²C-bus Control Mode (I2C pin = “H”)
The AK4372 supports fast-mode I²C-bus (max: 400kHz, Version 1.0).
(2)-1. WRITE Operations
Figure 41 shows the data transfer sequence for the I²C-bus mode. All commands are preceded by START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates START condition (Figure 47). After the START
condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W).
The most significant six bits of the slave address are fixed as “001000”. The next bit is CAD0 (device address bit). This
bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets this device address bit (Figure 42).
If the slave address matches that of the AK4372, the AK4372 generates an acknowledgement and the operation is
executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the
acknowledge clock pulse (Figure 48). A R/W bit value of “1” indicates that the read operation is to be executed. A “0”
indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4372. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 43). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 44). The AK4372 generates an acknowledgement after each byte is received. A data transfer is always
terminated by STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH
defines STOP condition (Figure 47).
The AK4372 can perform more than one byte write operation per sequence. After receiving the third byte the AK4372
generates an acknowledgement and awaits the next data. The master can transmit more than one byte instead of
terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit
address counter is incremented by one, and the next data is automatically taken into the next address. If the address
exceeds 13H prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will
be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW(Figure 49) except for the START and STOP
conditions.
S
T
S
A
R/W="0"
T
R
O
T
P
SDA
Slave
S _Address
Sub
Address(n)
Data(n)
Data(n+1)
Data(n+x)
P
A
A
A
A
A
A
C
C
C
C
C
C
K
K
K
K
K
K
Figure 41. Data Transfer Sequence at the I²C-Bus Mode
0
0
1
0
0
0 CAD0 R/W
(Those CAD0 should match with CAD0 pin)
Figure 42. The First Byte
0
0
0
A4
A3
A2
A1
A0
Figure 43. The Second Byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 44. Byte Structure after the second byte
MS0684-E-02
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2008/12