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AK4372 Datasheet, PDF (37/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP | |||
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[AK4372]
3) LIN/RIN/MIN â HP-Amp
Power Supply
PDN pin
PMVCM bit
(1) >150ns
(2) >0s
LINHL, MINHL,
RINHR, MINHR bits
(3) >0s
PMHPL/R bits
(5) >2ms
Donât care
(5) >2ms
MUTEN bit
LIN/RIN/MIN pins
HPL/R pins
(4)
(Hi-Z)
(6)
(Hi-Z)
(7)
(6)
Figure 30. Power-up/down sequence of LIN/RIN/MIN and HP-Amp
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. The PDN pin should be set to âHâ at least 150ns after power is supplied. MCKI, BICK and LRCK can be
stopped when DAC is not used.
(2) PMVCM bit should be changed to â1â after the PDN pin is set to âHâ.
(3) LINHL, MINHL, RINHR and MINHR bits should be changed to â1â after PMVCM bit is changed to â1â.
(4) When LINHL, MINHL, RINHR or MINHR bit is changed to â1â, the LIN, RIN or MIN pin is biased to 0.475 x
AVDD.
(5) PMHPL, PMHPR and MUTEN bits should be changed to â1â at least 2ms (in case external capacitance at the VCOM
pin is 2.2μF) after LINHL, MINHL, RINHR and MINHR bits are changed to â1â.
(6) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to
VCOM/2 is tr = 70k x C(typ). When C=1μF, tr = 70ms(typ).
(7) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to
VCOM/2 is tf = 60k x C(typ). When C=1μF, tf = 60ms(typ).
PMHPL and PMHPR bits should be changed to â0â after the HPL and HPR pins settle to VSS1. After that, the
LINHL, MINHL, RINHR and MINHR bits should be changed to â0â.
MS0684-E-02
- 37 -
2008/12
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