AK4372 Datasheet, PDF (51/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4372]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
Register Name
Power Management 0
PLL Control
Clock Control
Mode Control 0
Mode Control 1
DAC Lch ATT
DAC Rch ATT
Headphone Out Select 0
Lineout Select 0
Lineout ATT
Reserved
Reserved
Reserved
Headphone Out Select 1
Headphone ATT
Lineout Select 1
Mono Mixing
Differential Select
Reserved
Reserved
D7
0
FS3
PLL4
0
ATS
ATTL7
ATTR7
HPG1
0
0
0
0
0
0
0
0
0
0
0
0
D6
PMPLL
FS2
0
MONO1
DATTC
ATTL6
ATTR6
HPG0
LOG
0
0
0
0
0
HPZ
0
0
0
0
0
D5
PMLO
FS1
M/S
MONO0
LMUTE
ATTL5
ATTR5
MINHR
MINR
0
0
0
0
0
HMUTE
0
0
0
0
0
D4
MUTEN
FS0
MCKAC
BCKP
SMUTE
ATTL4
ATTR4
MINHL
MINL
0
0
0
0
0
ATTH4
0
0
0
0
1
D3
PMHPR
PLL3
BF
LRP
BST1
ATTL3
ATTR3
RINHR
RINR
ATTS3
0
0
0
0
ATTH3
0
0
0
0
0
D2
PMHPL
PLL2
PS0
DIF2
BST0
ATTL2
ATTR2
LINHL
LINL
ATTS2
0
0
0
0
ATTH2
0
0
0
0
0
D1
PMDAC
PLL1
PS1
DIF1
DEM1
ATTL1
ATTR1
DARHR
DARR
ATTS1
0
0
0
LINHR
ATTH1
LINR
LM
LDIFH
0
0
D0
PMVCM
PLL0
MCKO
DIF0
DEM0
ATTL0
ATTR0
DALHL
DALL
ATTS0
0
0
0
RINHL
ATTH0
RINL
LHM
LDIF
0
0
All registers inhibit writing at PDN pin = “L”.
PDN pin = “L” resets the registers to their default values.
For addresses from 14H to 1FH, data must not be written.
Unused bits indicated by “0” must contain a “0” value.
Unused bits indicated by “1” must contain a “1” value.
MS0684-E-02
- 51 -
2008/12