AK4372 Datasheet, PDF (17/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4372]
■ PLL Mode (PMPLL bit = “1”)
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL4-0 and FS3-0 bits (Table 4, Table 5, Table 6). The PLL lock time is shown in Table 4, whenever the AK4372 is
supplied to a stable clocks after PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes.
1) Setting of PLL Mode
Mode PLL4 PLL3 PLL2 PLL1 PLL0 Reference Clock
fs
R,C at VCOC
(Note 31) _{R[Ω] C[F]}
0
0
0
0
0
0 MCKI 11.2896MHz Type 1 10k 22n
1
0
0
0
0
1 MCKI 14.4MHz Type 1 10k 22n
2
0
0
0
1
0 MCKI 12MHz
Type 1 10k 47n
3
0
0
0
1
1 MCKI 19.2MHz Type 1 10k 22n
4
0
0
1
0
0 MCKI 15.36MHz Type 1 10k 22n
5
0
0
1
0
1 MCKI 13MHz
Type 1 15k 330n
6
0
0
1
1
0 MCKI 19.68MHz Type 1 10k 47n
7
0
0
1
1
1 MCKI 19.8MHz Type 1 10k 47n
8
0
1
0
0
0 MCKI 26MHz
Type 1 15k 330n
9
0
1
0
0
1 MCKI 27MHz
Type 1 10k 47n
10 0
1
0
1
0 MCKI 13MHz
Type 2 10k 22n
11 0
1
0
1
1 MCKI 26MHz
Type 2 10k 22n
12 0
1
1
0
0 MCKI 19.8MHz Type 3 10k 22n
13 0
1
1
0
1 MCKI 27MHz
Type 4 10k 22n
14 0
1
1
1
0 BICK
32fs
Table 6 6.8k 47n
15 0
1
1
1
1 BICK
64fs
Table 6 6.8k 47n
16 1
0
0
0
0 LRCK
fs
Table 6 6.8k 330n
Others Others
N/A
Note 31. Refer to Table5 about Type1-4
Note 32 : Clock jitter is lower in Mode10-13 than Mode5/ 7/ 8/ 9 respectively
Note 33. Modes 14~16 are available at Slave Mode only.
Table 4. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available)
PLL Lock
Time (typ)
20ms
20ms
20ms
20ms
20ms
100ms
20ms
20ms
100ms
20ms
20ms
20ms
20ms
20ms
20ms
20ms
80ms
(default)
2) Setting of sampling frequency in PLL Mode
When PLL reference clock input is MCKI pin, the sampling frequency is selected by FS3-0 bits as defined in Table 5.
Mode FS3 FS2 FS1 FS0
Type 1
fs
Type 2
Type 3
Type 4
0
0000
48kHz 48.0007kHz 47.9992kHz 47.9997kHz
1
0001
24kHz 24.0004kHz 23.9996kHz 23.9999kHz
2
0010
12kHz 12.0002kHz 11.9998kHz 11.9999kHz
4
0100
32kHz 32.0005kHz 31.9994kHz 31.9998kHz
5
0101
16kHz 16.0002kHz 15.9997kHz 15.9999kHz
6
0110
8kHz
8.0001kHz 7.9999kHz 7.9999kHz
8
1 0 0 0 44.1kHz 44.0995kHz 44.0995kHz 44.0995kHz (default)
9
1 0 0 1 22.05kHz 22.0498kHz 22.0498kHz 22.0498kHz
10
1 0 1 0 11.025kHz 11.0249kHz 11.0249kHz 11.0249kHz
3, 7,
11-15
Others
N/A
N/A
N/A
N/A
Table 5. Setting of Sampling Frequency (PLL reference clock input is the MCKI pin) (N/A: Not available)
MS0684-E-02
- 17 -
2008/12