AK4371 Datasheet, PDF (59/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4371]
SYSTEM DESIGN
Figure 45 shows the system connection diagram. An evaluation board [AKD4371] is available which demonstrates the
optimum layout, power supply arrangements and measurement results.
Analog Supply
1.6∼3.6V
+ _10µ
220µ
+
16Ω 16Ω
+
220µ
Headphone
Handsfree
0.1µ _0.22µ
2.2µ
0.1µ
+
Speaker
SPK-Amp
25 HPR
26 HPL
27 RIN2
28 LIN2
29 RIN3
30 LIN3
31 RIN1
32 LIN1
AK4371VN
Top View
MUTET 16
1µ
I2C 15
PDN 14
CSN 13
CCLK 12
CDTI 11
MCKO 10
VSS3 9
Rp
10
Cp
Analog Ground
Digital Ground
Audio Controller
µP
Notes:
- VSS1, VSS2 and VSS3 of the AK4371 should be distributed separately from the ground of external controllers.
- All digital input pins (I2C, SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN) must
not be left floating.
- When the AK4371 is in EXT mode (PMPLL bit = “0”), a resistor and capacitor for the VCOC pin is not needed.
- When the AK4371 is in PLL mode (PMPLL bit = “1”), a resistor and capacitor for the VCOC pin should be
connected as shown in Table 4
- When the AK4371 is used in master mode, LRCK and BICK pins are floating before the M/S bit is changed to
“1”. Therefore, a 100kΩ pull-up resistor should be connected to the LRCK and BICK pins of the AK4371.
- When DVDD is supplied from AVDD via 10Ω series resistor, the capacitor larger than 0.1μF should not be
connected between DVDD and the ground.
Figure 45. Typical Connection Diagram (In case of AC coupling to MCKI)
MS0596-E-00
- 59 -
2007/04