AK4371 Datasheet, PDF (26/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4371]
■ Serial Data Interface
The AK4371 interfaces with external systems via the SDATA, BICK and LRCK pins. Five data formats are available,
selected by setting the DIF2, DIF1 and DIF0 bits (Table 16). Mode 0 is compatible with existing 16-bit DACs and digital
filters. Mode 1 is a 20-bit version of Mode 0. Mode 4 is a 24-bit version of Mode 0. Mode 2 is similar to AKM ADCs and
many DSP serial ports. Mode 3 is compatible with the I²S serial data protocol. In Modes 2 and 3 with BICK≥48fs, the
following formats are also valid: 16-bit data followed by eight zeros (17th to 24th bits) and 20-bit data followed by four
zeros (21st to 24th bits). In all modes, the serial data is MSB first and 2’s complement format.
When master mode and BICK=32fs(BF bit = “0”), the AK4371 cannot be set to Mode 1 Mode 2 or Mode 4.
Mode
0
1
2
3
4
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
0
1
0
1
0
Format
BICK
0: 16bit, LSB justified
32fs ≤ BICK ≤ 64fs
1: 20bit, LSB justified
40fs ≤ BICK ≤ 64fs
2: 24bit, MSB justified
48fs ≤ BICK ≤ 64fs
3: I²S Compatible BICK=32fs or 48fs ≤ BICK ≤ 64fs
4: 24bit, LSB justified
48fs ≤ BICK ≤ 64fs
Table 16. Audio Data Format
Figure
Figure 17
Figure 18
Figure 19
Figure 20
Figure 18
(default)
LRCK
BICK
(32fs)
SDATA
Mode 0
BICK
15 14
6 5 4 3 2 1 0 15 14
6 5 4 3 2 1 0 15 14
SDATA
Mode 0
Don’t care
15:MSB, 0:LSB
15 14
0 Don’t care
15 14
0
Lch Data
Rch Data
Figure 17. Mode 0 Timing (LRP = BCKP bits = “0”)
LRCK
BICK
SDATA
Mode 1
Don’t care
19:MSB, 0:LSB
19
0 Don’t care
19
0
SDATA
Don’t care 23 22 21 20 19
0 Don’t care 23 22 21 20 19
0
Mode 4
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 18. Mode 1, 4 Timing (LRP = BCKP bits = “0”)
MS0596-E-00
- 26 -
2007/04