AK4371 Datasheet, PDF (13/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4371]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, PVDD, HVDD=1.6 ∼ 3.6V; C_L = 20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max Units
Master Clock Input Timing
Frequency (PLL mode)
fCLK
11.2896
-
27
MHz
(EXT mode)
fCLK
2.048
-
24.576 MHz
Pulse Width Low (Note 24)
tCLKL
0.4/fCLK
-
-
ns
Pulse Width High (Note 24)
tCLKH
0.4/fCLK
-
-
ns
AC Pulse Width (Note 25)
tACW
18.5
-
-
ns
LRCK Timing
Frequency
Duty Cycle: Slave Mode
fs
Duty
8
44.1
48
kHz
45
-
55
%
Master Mode
Duty
-
50
-
%
MCKO Output Timing (PLL mode)
Frequency
fCLKO
0.256
-
12.288 MHz
Duty Cycle (Except fs=32kHz, PS1-0= “00”)
dMCK
40
-
60
%
(fs=32kHz, PS1-0= “00”)
dMCK
-
33
-
%
Serial Interface Timing (Note 26)
Slave Mode (M/S bit = “0”):
BICK Period (Note 27)
(Except PLL Mode, PLL4-0 = “EH”, “FH”) tBCK 312.5 or 1/(64fs)
- 1/(32fs) ns
(PLL Mode, PLL4-0 bits = “EH”)
tBCK
-
1/(32fs) -
ns
(PLL Mode, PLL4-0 bits = “EH”)
tBCK
-
1/(64fs) -
ns
BICK Pulse Width Low
(Except PLL Mode, PLL4-0 = “EH”, “FH”) tBCKL
100
-
-
ns
(PLL Mode, PLL4-0 bits = “EH”, “FH”)
tBCKL
0.4 x tBCK
-
-
ns
BICK Pulse Width High
(Except PLL Mode, PLL4-0 = “EH”, “FH”) tBCKL
100
-
-
ns
(PLL Mode, PLL4-0 bits = “EH”, “FH”)
tBCKH
0.4 x tBCK
-
-
ns
LRCK Edge to BICK “↑” (Note 28)
BICK “↑” to LRCK Edge (Note 28)
tLRB
50
tBLR
50
-
-
ns
-
-
ns
SDATA Hold Time
tSDH
50
-
-
ns
SDATA Setup Time
tSDS
50
-
-
ns
Master Mode (M/S bit = “1”):
BICK Frequency (BF bit = “1”)
fBCK
-
64fs
-
Hz
(BF bit = “0”)
fBCK
-
32fs
-
Hz
BICK Duty
dBCK
-
50
-
%
BICK “↓” to LRCK
tMBLR
−50
-
50
ns
SDATA Hold Time
tSDH
50
-
-
ns
SDATA Setup Time
tSDS
50
-
-
ns
Control Interface Timing (3-wire Serial mode)
CCLK Period
tCCK
200
-
-
ns
CCLK Pulse Width Low
tCCKL
80
-
-
ns
Pulse Width High
tCCKH
80
-
-
ns
CDTI Setup Time
tCDS
40
-
-
ns
CDTI Hold Time
tCDH
40
-
-
ns
CSN “H” Time
tCSW
150
-
-
ns
CSN “↑” to CCLK “↑”
tCSS
50
-
-
ns
CCLK “↑” to CSN “↑”
tCSH
50
-
-
ns
Note 24. Except AC coupling.
Note 25. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to
ground. Refer to Figure 3.
Note 26. Refer to “Serial Data Interface”.
Note 27. Min is longer value between 312.5ns or 1/(64fs) except for PLL Mode, PLL4-0 bits = “EH”, “FH”.
Note 28. BICK rising edge must not occur at the same time as LRCK edge.
MS0596-E-00
- 13 -
2007/04