AK4371 Datasheet, PDF (5/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4371]
PIN/FUNCTION
No. Pin Name I/O
Function
1 SDATA
I Audio Serial Data Input Pin
2 BICK
I/O Audio Serial Data Clock Pin
3 LRCK
I/O Input / Output Channel Clock Pin
4 MCKI
I External Master Clock Input Pin
5 DVDD
- Digital Power Supply Pin, 1.6 ∼ 3.6V
6 PVDD
- Power Supply for PLL, 1.6 ∼ 3.6V. Normally connected to AVDD.
7 VCOC
O
Output for Loop Filter of PLL Circuit
This pin should be connected to VSS3 with one resistor and one capacitor in series.
8 VSS2
- Ground Pin
9 VSS3
- Ground Pin
10 MCKO
O Master Clock Output Pin
11 ^SDA
CDTI
I/O Control Data Input/Output Pin (I2C mode : I2C pin = “H”)
I Control Data Input Pin (3-wire serial mode : I2C pin = “L”)
12 ^SCL
CCLK
I Control Data Clock Pin (I2C mode : I2C pin = “H”)
I Control Data Clock Pin (3-wire serial mode : I2C pin = “L”)
13
CAD0
CSN
I Chip Address 0 Select Pin (I2C mode : I2C pin = “H”)
I Chip Select Pin (3-wire serial mode : I2C pin = “L”)
Power-down & Reset
14 PDN
I
When “L”, the AK4371 is in power-down mode and is held in reset.
The AK4371 should always be reset upon power-up.
15 I2C
I
Control Mode Select Pin
“H”: I²C Bus, “L”: 3-wire Serial
16 MUTET
O
Mute Time Constant Control pin
Connected to VSS1 pin with a capacitor for mute time constant.
17 MOUT
O Mono Signal Output Pin
18 LOUT
O Lch Stereo Line Output Pin
19 ROUT
O Rch Stereo Line Output Pin
20 VREF
O
Reference Voltage Output Pin
Normally connected to VSS1 pin with a 0.22μF electrolytic capacitor.
21 VCOM
O
Common Voltage Output Pin
Normally connected to VSS1 pin with a 2.2μF electrolytic capacitor.
22 AVDD
- Analog Power Supply Pin, 1.6 ∼ 3.6V
23 HVDD
- Power Supply Pin for Headphone Amp, 1.6 ∼ 3.6V
24 VSS1
- Ground Pin
25 HPR
O Rch Headphone Amp Output
26 HPL
O Lch Headphone Amp Output
27 RIN2
I Rch Analog Input 2 Pin
28 LIN2
I Lch Analog Input 2 Pin
29 RIN3
I Rch Analog Input 3 Pin
30 LIN3
I Lch Analog Input 3 Pin
31 ^RIN1
IN+
I Rch Analog Input 1 Pin (LDIF bit =“0” : Single-ended Input)
I Positive Line Input Pin (LDIF bit =“1” : Full-differential Input)
32 ^LIN1
IN−
I Rch Analog Input 1 Pin (LDIF bit =“0” : Single-ended Input)
I Negative Line Input Pin (LDIF bit =“1” : Full-differential Input )
Note 1. All digital input pins (I2C, SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN) must not
be left floating. MCKI pin can be left floating only when PDN pin = “L”.
MS0596-E-00
-5-
2007/04