AK4371 Datasheet, PDF (42/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4371]
5) LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 → Lineout
Power Supply
PDN pin
PMVCM bit
LIN1L, RIN1R,
LIN2L, RIN2R,
LIN3L, RIN3R bits
PMLO bit
(1) >150ns
(2) >0s
(3) >0s
(5) >2ms
Don’t care
(5) >2ms
LIN1/RIN1/
LIN2/RIN2/
LIN3/RIN3 pins
LMUTE,
ATTS3-0 bits
(4)
(Hi-Z)
10H(MUTE)
0FH(0dB)
(Hi-Z)
(6)
LOUT/ROUT pins
(Hi-Z)
(6)
(6)
(Hi-Z)
Figure 33. Power-up/down sequence of LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 and Lineout
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. When AVDD and HVDD are supplied separately, AVDD should be powered-up at the same time or earlier
than HVDD. PDN pin should be set to “H” at least 150ns after power is supplied. MCKI, BICK and LRCK can be
stopped when DAC is not used.
(2) PMVCM bit should be changed to “1” after PDN pin goes “H”.
(3) LIN1L, LIN2L, LIN3L, RIN1R, RIN2R and RIN3R bits should be changed to “1” after PMVCM bit is changed to
“1”.
(4) When LIN1L, LIN2L, LIN3L, RIN1R, RIN2R or RIN3R bit is changed to “1”, LIN1, RIN1, LIN2, RIN2, LIN3 or
RIN3 pin is biased to 0.475 x AVDD.
(5) PMLO bit should be changed to “1” at least 2ms (in case external capacitance at VCOM pin is 2.2μF) after LIN1L,
LIN2L, LIN3L, RIN1R, RIN2R and RIN3R bits are changed to “1”.
(6) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins.
MS0596-E-00
- 42 -
2007/04