AK4371 Datasheet, PDF (21/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4371]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 13MHz, 14.4MHz, 15.36MHz, 19.2MHz, 19.68MHz,19.8MHz, 26MHz
or 27MHz) is input to MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The
MCKO output frequency is selected by PS1-0 bits (Table 9) and the output is enabled by MCKO bit. The BICK output
frequency is selected between 32fs or 64fs, by BF bit (Table 10).
AK4371
MCKI
MCKO
BICK
LRCK
SDATA
27MHz,26MHz,19.8MHz,19.68MHz,
19.2MHz,15.36MHz,14.4MHz,13MHz,
12MHz,11.2896MHz
DSP or μP
256fs/128fs/64fs/32fs
32fs, 64fs
1fs
MCLK
BCLK
LRCK
SDTO
Figure 11. PLL Master Mode
PS1
PS0
MCKO
0
0
256fs (default)
0
1
128fs
1
0
64fs
1
1
32fs
Table 9. MCKO Frequency (PLL mode, MCKO bit = “1”)
BF bit
BICK Frequency
0
32fs
(default)
1
64fs
Table 10. BICK Output Frequency at Master Mode
MS0596-E-00
- 21 -
2007/04