AK4371 Datasheet, PDF (35/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4371]
■ Stereo Line Output (LOUT, ROUT pins)
The common voltage is 0.475 x AVDD. The load resistance is 10kΩ(min). When the PMLO bit is “1”, the stereo line
output is powered-up. DALL, LIN1L, RIN1L, LIN2L, RIN2L, LIN3L and RIN3L bits control each path switch of LOUT.
DARR, LIN1R, RIN1R, LIN2R, RIN2R, LIN3R and RIN3R bits control each path switch of ROUT. When L1M = L2M
= L3M bits = “0”, LOG bit = “0” (R_1L = R_2L = R_3L= R_DL = 100k) and ATTS3-0 bits is “0FH”(0dB), the mixing gain is
0dB(typ) for all paths. When the LOG bit = “1”(R_DL= 50k), the DAC path gain is +6dB. When L1M = L2M = L3M bits =
“1”, LIN1/RIN1, LIN2/RIN2 and LIN3/RIN3 signals are output from LOUT/ROUT pins as (L+R)/2 respectively (R_1L=
R_2L= R_3L = 200k).
If the path is OFF and the signal is input to the input pin, the input pin should be biased to a voltage equivalent to VCOM
voltage (= 0.475 x AVDD) externally. Figure 46 shows the external bias circuit example.
LIN1 pin
RIN1 pin
LIN2 pin
RIN2 pin
LIN3 pin
RIN3 pin
DAC Lch
R1L
LIN1L bit
R1L
RIN1L bit
R2L
LIN2L bit
R2L
RIN2L bit
R3L
LIN3L bit
R3L
RIN3L bit
RDL
DALL bit
100k(typ)
−
RL
+
RL
−
+
LOUT pin
LIN1 pin
RIN1 pin
LIN2 pin
RIN2 pin
LIN3 pin
RIN3 pin
DAC Rch
R1L
LIN1R bit
R1L
RIN1R bit
R2L
LIN2R bit
R2L
RIN2R bit
R3L
LIN3R bit
R3L
RIN3R bit
RDL
DARR bit
100k(typ)
−
RL
+
RL
−
+
ROUT pin
Figure 26. Summation circuit for stereo line output
MS0596-E-00
- 35 -
2007/04